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F453 Computer Architectures Flashcards | StudBud
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F453 Computer Architectures
F453 Computer Architectures
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Memes and F453 Computer Architectures Quiz
Flashcards
21 cards
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Questions
21
Answers
1
The Von Neumann Architecture Processes _____ ________ at a time.
many instructions
one instruction
many data points
one data point
2
What is flags?
A register.
A type of interrupt.
A collection of boolean bits.
3
Reduced Instruction Set ___________?
Coding
Computer
Computing
Coordination
4
Pick an advantage of a Co-Processor
Run complex mathematical operations faster
Able to run multiple parts of a program simaultaneously
Sweet graphics
Reduces disk threshing
5
In the Von Neumann architecture, data and instructions are...
Stored in the same format
Stored together in ROM
Stored in the same memory
Sent on the same bus
6
NVIDIA and AMG make...
Parallel Processors
Co-Processors
Batch Processors
CPUs
7
RISC instructions often take multiple clock cycles to complete...
True
False
8
I want to run an intensive simulation...
Use an array processor!
Use a Parallel Processor!
Use a Von Neumann processor!
Use a Co-Processor!
9
What is the machine cycle another name for?
The spooling cycle.
An instruction cycle.
A clock cycle.
Fetch Decode Execute cycle.
10
Which of these is not a type of processor?
Parallel
Array
Co
Joint
11
BONUS ROUND 1: A compact parallel processor is...
An integrated processor
A microprocessor
A multiprocessor
12
Comic Sans Is the Worst Font Ever.
F.alse
False
False
False
13
In a CISC architecture...
There are few instructions.
...a process will take multiple instructions.
...each instruction takes less time to complete.
...the processor costs more.
14
Which of these is not a step of the FDE cycle?
Address in MAR is copied to MDR
PC is incremented.
Instruction in MDR is copied to CIR.
15
What if I told you that was Falco?
No
Dank Memes
qasfuiawJKSBFUKL\JQW90UJ
Rage
16
BONUS ROUND! ARE YOU READY TO RUMBLE?
No
Yes
17
One of these is not like the others...
Encode
Fetch
Execute
Decode
18
One of these is not like the others...
CIR
DMR
IR
MAR
19
BONUS ROUND 2: Graphics, Intensive, Repetetive
Co, Parallel, Array
Von Neumann
Parallel, Array, Co
20
BONUS ROUND 3: GOT TO GO FAST!
RISC
CISC
21
State an advantage of CISC over RISC.
More clock cycles required per instruction.
Less clock cycles required per instruction.
Less instructions required to complete a task.
Less tasks needed per instruction.
