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Final review
Final review
70 terms
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Practice quiz
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Questions
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Answers
1
Serial interfaces use fewer pins and wires than parallel interfaces.
False
True
2
When the processor detects that the ADC has signaled completion by asserting INTR, what does it do next?
It de-asserts CS and WR
It resets the ADC
It re-asserts CS to restart conversion
It asserts the RD (read) signal to read data from D0–D7
3
After the processor asserts CS and WR, what does the ADC do once it completes conversion?
It asserts RD (read)
It resets its data lines
It asserts INTR (interrupt), signaling that data is ready to be read
It de-asserts CS
4
Why is DRAM generally cheaper per bit than SRAM?
Uses only 1 transistor and 1 capacitor per cell
Has built-in sense amplifiers in each cell
Use 6 transistors but cheaper one
Uses more transistors per cell but simpler layout
5
When the total CPU utilization is smaller than 1, which of the following can be said about
Earliest Deadline First (EDF)
EDF requires more resources than RMS
EDF cannot work if the utilization is below 50%
EDF cannot schedule the task set
EDF can schedule the task set
6
Bare metal execution typically results in faster performance than OS-assisted execution(similar hardware configurations)
True
False
7
On the SiFive watchdog, which register must you write the magic key 0x51F15E into before touching any other WDT?
wdogkey
wdogfeed
wdogcfg
wdogcmp
8
Which flash technology is most commonly found in solid-state drives (SSDs) for data storage?
DRAM
NAND flash
NOR flash
EEPROM
9
When the processor decides to read from the ADC, which signals must it assert(set to 0) to start the conversion process?
WR and RD
RD only
CS only
CS and WR
10
Which statement best describes the CPU’s behavior when an interrupt is signaled during instruction execution?
The CPU must complete the current stage before beginning interrupt
The CPU immediately stops mid-stage to service the interrupt
The CPU ignores the interrupt until the 5 stage execution is done
The CPU flushes the entire pipeline and then services the interrupt.
11
Which statement correctly compares NAND and NOR flash regarding read/write performance?
NOR flash: fast random reads, NAND flash: slower random reads/faster writes
NOR flash is typically only used for bulk data writes.
NAND flash: fast random reads, NOR flash : slow random reads
Both NAND and NOR flash have identical random read performance.
12
Bare metal execution is faster than OS-assisted execution(assuming similar hardware configurations).
False
True
13
For
RMS
, if the total CPU utilization < the Liu and Layland bound, the task set is guaranteed to be schedulable
False
True
14
What happens during a
context switch
in an operating system?
The process is removed from memory.
The CPU switches between processes or threads to allow multitasking.
The CPU switches from running one program to another.
The program completes and the OS terminates it.
15
Which operator performs a
bitwise OR
, combining two values one bit at a time?
|
&&
||
&
16
Which of the following is a key feature of an operating system?
It manages only memory and storage.
It handles application logic.
It provides a user interface and manages hardware resources.
It only manages processes.
17
Which scenario best represents a CPU-bound process?
Continuously processing complex mathematical computations
Transferring data over a network
Waiting for user input
Waiting for data from a hard drive
18
Main difference between Rate Monotonic Scheduling (RMS) and Earliest Deadline First (EDF) in real-time operating systems
EDF only handles periodic tasks, RMS handles both periodic and aperiodic
RMS assigns priority based on deadlines, while EDF uses task periods.
RMS uses fixed priorities, EDF assigns priorities based on task deadlines
RMS is for hard real-time systems, EDF for soft real-time systems.
19
A watchdog timer must be “kicked” (reset) periodically by the CPU code or it will reset the processor.
True
False
20
Which scenario best justifies using a DAC instead of PWM?
Generating a noise‑free audio waveform
Minimizing component cost
Driving a high‑torque motor efficiently
Implementing simple on/off control
21
Which of the following statements about flash memory is true?
It has limited write cycles, so wear leveling and buffering are used
It has unlimited write cycles so no special techniques are needed
It is designed to be written only once
It's write cycles can be increased by reducing the operating voltage
22
CAN bus is best described as:
A USB-like host/device tree topology
A multi-master, differential, broadcast network
A point-to-point, half-duplex serial link
A single-master, synchronous protocol
23
A digital-to-analog converter is used to convert the analog signal from a microphone into a digital file on a computer
False
True
24
Which C operator is the
dereference
operator, used to access the value at the address held by a pointer?
&
*
>>
%
25
Which motor provides precise angular position control using feedback?
Brushed DC
Servo motor
Induction
Brushless DC
26
Knowing that: t1(e = 6, p = 15), t2(e = 2, p = 5), t3 (e = 2, p = 8). Which task missed the deadline here?
t2
t3
t1
27
Which technique is used to manage the limited write cycles of flash memory?
Dynamic clock scaling
Bit shifting
Wear leveling
Voltage scaling
28
Temporal locality: If a program accesses a memory location, it is likely to access that same location again shortly.
True
False
29
What is the primary function of a bootloader in embedded systems?
Run user applications
Handle interrupts
Manage power consumption
Initialize hardware and load the main app
30
After any DRAM read, what must happen to the cell to preserve its data?
It must be restored/refreshed
It must be inverted
It must be pre-charged
It can be left as is
31
A task set with CPU utilization greater than 1 is always schedulable under EDF but not RMS.
False
True
32
What does the wdogcmp register hold?
Scale factor
Current counter value
Compare/timeout threshold
Feed (kick) address
33
Parallel communication is faster than serial communication because multiple bits are transmitted simultaneously.
False
True
34
Spatial locality: If a memory location is accessed, its neighboring locations are likely to be accessed soon.
False
True
35
Which motor advances in discrete, fixed‑angle increments without feedback?
AC induction
Universal
Servo
Stepper motor
36
A
closed‑loop
control system relies on:
Feedback from a sensor
Manual calibration
Pre-programmed steps
External clock
37
Which best describes an
open‑loop
control system?
Requires a sensor
Uses feedback to adjust output
Only works with PWM
Has no feedback mechanism
38
What is something that is stored in memory,but not actively running and only exists as instructions to be executed later
A program
A thread
A process
An interrupt
39
Which of the following transfer types allows data to be sent in both directions simultaneously?
Single-Direction
Simplex
Full-Duplex
Half-Duplex
40
You can do multi-threaded processes using bare metal systems.
False
True
41
What's the priority of interruptions A, B and C
B < C < A
A > B > C
A < B < C
A < C < B
42
When you read a stored “1” from a DRAM cell, what happens to its capacitor?
Nothing happened
It fully discharges
It overcharges
It slightly discharges
43
Which of the following best describes serial communication?
Data is transmitted over long distances using high-speed signals.
Data is transmitted simultaneously across multiple wires.
Data is transmitted without the use of a clock signal.
Data is transmitted one bit at a time, over a single wire.
44
Knowing that: t1(e = 6, p = 15), t2(e = 2, p = 5), t3 (e = 2, p = 8). Which task missed the deadline here?
t1
t2
t3
45
An ADC is used to convert analog signals from sensors into digital data that can be processed by a computer.
False
True
46
Which communication methods is data sent one bit at a time, with a clock signal coordinating the timing of transmission?
Bluetooth communication
Synchronous communication
Asynchronous communication
Parallel communication
47
What is the difference between an interrupt and an exception?
Interrupts are from external events; exceptions arise from internal errors
Interrupts occur during the fetch stage, exceptions occur during execution.
Exceptions are from external events, interrupts come from within the CPU.
Interrupts and exceptions are identical events.
48
Which statement best describes a key requirement for an ISR (Interrup Service Routine)?
It can ignore preserving register values.
It should perform lengthy computations.
It must quickly handle events and return control to the main program.
It should disable all interrupts until complete.
49
Which of the following is NOT true about function pointers?
They can only point to functions that return void.
They allow a function to be passed as a parameter.
They store the memory address of a function with a matching signature.
They can be used to call a function indirectly.
50
Knowing that: t1(e = 6, p = 15), t2(e = 2, p = 5), t3 (e = 2, p = 8). Which one show rate monotonic scheduling?
Graph B
Graph A
51
If a program spends most of its execution time waiting for data from a hard drive, then it is considered CPU-bound.
False
True
52
If wdogscale = 5 on a 32.768 kHz clock, approximately how often does the watchdog counter tick?
976 µs
15.6 ms
61 µs
31.2 ms
53
Asynchronous communication: data is transmitted without a clock signal and relying on start and stop bits
True
False
54
Assume a stepper motor is designed for 1.5-degree step angles. How many steps per revolution will it have
120
180
360
240
55
Which of the following best defines a
thread
in an operating system?
A process that is currently running on the CPU.
A set of instructions that exists in memory but is not currently executing.
A single instruction being processed by the CPU.
A set of instructions that can be executed independently within a process
56
The bootloader is compiled
independently
of the main application.
True
False
57
A
process
is essentially a program that is currently being executed and managed by the operating system.
True
False
58
Interrupt service routines should execute promptly and return so that they don’t block the main application.
True
False
59
The priority of jobs can dynamically change with an earliestdeadline first (EDF) scheduler
False
True
60
What does the term “volatile” mean in the context of memory?
It retains data when power is removed
It loses data when power is removed
It has unlimited write cycles
It is used for permanent storage
61
In flash memory system, which of the following is NOT one of these techniques used to manage data and extend lifespan?
Wear leveling–ensure even distribution of write/erase cycles across memory
External data buffering–reduce number of write operations by buffering data
Frequency scaling–dynamically change the clock speed during operations
Data compression–reduce the volume of data by compressing it before storing
62
SPI communication does
not
include explicit start or stop bits in its bus protocol.
False
True
63
Interrupt service routines are called explicitly from the main program executing.
False
True
64
Which of the following statement is true: If Liu and Layland bound <
the CPU utilization
< 1 ?
The task set is schedulable under EDF but not under RMS
The task set is schedulable under RMS but not under EDF
Both EDF and RMS can schedule the task set.
The task set is unschedulable under both RMS and EDF.
65
What is
Secure Boot
primarily responsible for?
Managing user passwords
Speeding up startup
Handling file transfers
Ensuring only trusted code loads
66
In an interrupt-driven system, the CPU checks the I/O status bits in a loop until the device is ready to be serviced.
False
True
67
Which statement best explains the difference between direct mode and vectored interrupts?
Direct is software-triggered, while vectored is hardware-triggered.
Direct is FIFO, while vectored is prioritized.
Direct requires polling, while vectored does not.
Direct uses one common handler; vectored jumps to specific handlers.
68
Main difference between Rate Monotonic Scheduling (RMS) and Earliest Deadline First (EDF) in real-time operating systems
RMS uses fixed priorities, EDF assigns priorities based on task deadlines
RMS assigns priority based on deadlines, while EDF uses task periods.
RMS is for hard real-time systems, EDF for soft real-time systems.
EDF only handles periodic tasks, RMS handles both periodic and aperiodic
69
Which of these best describes SPI?
4-wire full-duplex protocol
1-wire serial protocol
2-wire synchronous protocol
3-wire half-duplex protocol
70
What does PWM vary to control DC motor speed?
Frequency
Amplitude
Duty cycle
Phase
