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Chapter 6
How can cache performance affect arithmetic intensity? (549)
In general, NVIDIA GPUs (552)
Chapter 6
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Chapter 6
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1
In general, NVIDIA GPUs (552)
Outperform Intel CPUs in raw GFLOPS
Are inferior devices when compared with Intel processors.
Don't have the memory bandwidth Intel processors have.
Branch instructions better than multi-core Intel processors.
2
How can cache performance affect arithmetic intensity? (549)
Allow the CPU direct access to lower-level cache.
By reducing power so the CPU clock can be sped up.
Reduce # of memory accesses, maintain the # of calculations.
It cannot be done.
3
What is the distinguishing feature of a crossbar network?
It uses very little power.
Any node can reach any other node in 1 pass through network.
It is essentially a double-ring network
It takes up the least space on a chip.
4
The Intel Core i7 processor often outperforms NVIDIA graphics cards b/c of the i7 design(552)
T
F
5
The Roofline model characterizes (544)
Compiler optimization
Hardware performance limitations
Graphics speed
Disk performance
6
Computers connected with a local area network all working on one task is called a(n) (502)
Group Computing Infrastructure
Cluster
Grid
Pod
7
A significant challenge in having multiple cores in a processor is (519)
Using them.
Using snooping protocol
Maintaining cache coherence
Keeping them from getting too hot.
8
The units for arithmetic intensity are (548)
FLOPS/Byte
GFLOPS/Sec
GB/sec
FLOPS/watt
9
A serial program can run on a parallel processor (503)
T
F
10
Netwrk w/4 links can handle different data at same time, total bandwidth=4x link bandwidth(537)
T
F
11
Which of the following features high arithmetic intensity? (543)
Matrix multiplication
Reading a little, calculating a lot.
Matrix inversion
Sparse matrix operations
12
The bandwidth between two equal parts of the processor is called the (527)
Bisection bandwidth
Network bandwidth
symbol rate
Crossbar bandwidth
13
Single instruction, multiple data applications operate like vector applications except (513)
They use much narrower registers (not as wide).
They have much faster memory access.
SIMD applications use very wide registers.
They consume more power.
14
Effective use of multiple processors requires (508)
Better debuggers.
Patience
More memory
Sharing the work effectively.
15
Bisection bandwidth is (537)
No longer an accurate measure of processor performance.
Network bandwidth.
Link bandwidth.
The bandwidth between two equal parts of the processor.
16
The roofline model of a processor with a larger number of cores than another processor (546)
Does not show performance gains over a uniprocessor.
Shows that the processor may more quickly overheat
Shows more significant memory limitations.
Can perform more FLOPs/Sec
17
A feature of software written for multiple processors allows for processors to fail (502)
F
T
18
A shared memory processor is (503)
A processor which can access the memory of other machines
A processor that does not have its own memory
Multiple processors addressing the same memory.
A computer that controls other computers to solve a problem
19
The opposite of symmetric multiprocessing is (523)
Vector processing
Fine-grained multithreading.
Simultaneous multithreading (SMT)
Where main memory isn't as accessible by some processors.
20
Coordinating behavior of 2+ processes which are running on different processors is called (520)
Synchronization
Snooping
Parsing
Clustering
21
Which best defines arithmetic intensity? (543)
FLOPs/Byte
FLOPs/operand.
The mission-criticality of the application
FLOPs/word
22
Cores are connected by (536)
Network topologies.
Cat-5 cable.
Fiber
PCI express busses.
23
How can the horizontal portion of the roofline performance model be raised (546)
More computing lanes.
Adding more memory
Adding more banks of memory
Performing multiple issue.
24
Benchmark performance has a significant effect on improvements made in new processors (554)
T
F
25
Because of modern design tools, any network that can be imagined can be created in silicon(538)
T
No way!
F
Heck yeah!
26
If a fully connected network has n nodes, how many links are there? (537)
n*2
n(n-1)/2
n/2
n^2
27
A programming problem, 1/2 of which is parallelizable can be sped up 5x with processors (506)
T
F
28
Tremendous performance gains can be made in multi-threaded architectures if (555)
Synchronization doesnot fail.
The problem to be solved can use the advances.
Cache coherence is maintained.
The compiler is smarter than the programmer.
29
What is the most efficient use of the processor? (517)
Simultaneous Multithreading
Course-grained multithreading
Fine-grained multithreading
Avoiding data stalls via forwarding
30
Dividing a 128-bit register to handle 4 single-precision calculations at once is exmple of(510)
Scalar processing
Multiple Instruction Multiple Data
Multiple issue.
SIMD
31
The simplest on-chip interconnection system is a(n) ____ (536)
Bus
PCI express interface.
Cube.
Ring.
32
A process that produces 1 result from multiple data, decreasing the size of the problem is(521)
Mapping
Miracle
Strip mining.
Reduction
33
Which of the following features low arithmetic intensity? (543)
Computational fluid dynamics
Reading a lot, calculating very little.
N-body astrodynamics problems
Weather prediction
34
Traditional benchmark restrictions limit performance gains to (542)
the architecture and compiler
cache and main memory access improvements
programmers and algorithms
the benchmark and the programmer
35
The performance of an app goes up by rewriting the app to fit the processor's strengths (558)
T
F
36
The concept of "lanes" in vector processing is (515)
Adding more hardware to do operations in parallel
Similar to reservation stations in scalar processing
Causing memory access to become an issue.
Efficient, but not cost-effective for most applications.
37
A bus broadcasts info to all listeners. A ring can make multiple simultaneous transfers (536)
F
T
38
A program which can be split into multiple, independent tasks features (502)
Robustness
Process-level parallelism
Dependability
Data-level parallelism
39
The vertical axis of the roofline model is (548)
Linear.
Quadratic
Cycles per instruction
GFLOPS/Sec
40
Most multiprocessor benchmark suites feature weak scaling (541)
T
F
41
Now that we have parallel processors, what's the problem? (504)
They take up too much power.
Their caches are not large enough.
Main memory is still expensive.
Lack of software that can effectively use the hardware.
42
Weak scaling algorithms artificially drive up the peak GFLOP performance of a processor (549)
T
F
43
Vetor processing can reduce code for vector/matrix manipulations by a factor of about (512)
10
2
There is not reduction.
100
44
Traditional rules of benchmark performance testing cause (542)
High accuracy in performance measurement.
Performance tests to be expensive.
Certain performance enhancements not to be tested.
Newer architecture to appear faster than they really are.
45
The essense of writing vector instructions in certian situations is to leverage (512)
Request-level parallelism
SIMD
Task-level parallelism
Thread-level parallelism
46
The slanted part of the roofline performance model represents (544)
Effects of the power wall.
Arithmetic precision limitations.
Processor can't get enough data to perform calculations.
Network I/O limitations
47
An app that reads memory and selectively performs calculations = high arithmetic intensity(543)
F
T
48
In order to get reliable results across benchmarks run on different systems... (540)
The test must be monitored by a certified proctor.
SPEC must run the tests.
Results are only published in English
The code cannot be changed.
49
Parallel programs can run equally well on serial processors (503)
F
T
50
Linpack is (540)
the name of an annual computer performance competition
A uniprocessor test suite.
Linear algebra routines for multirocessors.
the nickname for the open source coders working on Linux
51
The flat part of the roofline performance model represents (544)
Arithmetic precision limitations.
Effects of the power wall.
Where the processor can't perform calculations fast enough.
Memory bandwidth limitations
52
Roofline model apps whose arithmetic intensities are left of the graph's inflection point (559)
More cores are needed to improve efficiency.
More cores are needed to improve performance.
The processor will run hot.
They are memory bandwidth limited.
53
In the multiprocessor environment of the last 10 years (502)
Datawarehouse applications don't have the parallelism needed
Manufacturers long for the uniprocessor days.
Energy efficiency is no longer important.
Ideally, performance should scale with the # of processors.
54
Single-precision floating point calculation rate > double-precision calculation rate(552)
F
T
55
It isn't unusual for memory-bandwidth line in roofline performance model to have unequal slopes
T
F
56
The number of links in a fully connected network scales as (537)
n^2
a constanct
log n
n
