“push” and “pop” What is the correct way to specify memory address for these instructions?

SP is updated automatically, always have their address in Stack Pointer (SP)

what is stored in an ISA

number of registers, number of instructions

What does DMA (Direct Memory Access) enable?

DMA allows input/output devices to access memory without CPU intervention

Virtual memory Safety: how to enable safe and efficient sharing of memory among multiple programs?

To prevent user programs to access memory used by OS, control the access by one user program to the memory of other user programs

Memory locations close to a recently accessed location are likely to be

Which of the following first two statements is TRUE

Both of the first two statements are FALSE

fraction of accesses that are miss at a givn level of hierarchy(1-hit rate)

what is wrong about Pipelined processor design

Overlapping does not improve hardware utilization and performance

special instructions to access IO, mapped to separate memory, same as port-mapped IO

Which of the following is defined by Instruction Set Architecture (ISA)?

The register width (i.e. the number of bits in a register)

what is Von Neumann architecture

shared instruction and data memory

Why is the address bus unidirectional and the data bus is bidirectional?

Data needs to go in one direction for write and in the other for read

Dependencies and hazards are related concepts. Which of the following statements about them is true:

Dependencies occur in the instruction stream, hazards occur in the pipeline

In ARM assembly programming, a "mov" instruction can be used to move an immediate value, say 45, to a register, say r3

Can we move a value of 1024 to a register using this same instruction? NO

Read operands, Store result, Perform required operation

which is callee registers and wich is caller

r0 to r3 = caller r4 to r12 = callee

Machine dependent optimizations are aimed at a specific target architecture. Which?

All of the above are machine independent optimizations

Pipeline needs to be paused to avoid hazards, Cycle time in pipelined design is 1/3 of single cycle design

Hit/miss in the brackets indicates whether the access resulted in a hit or miss in that structure.

TLB(hit) -> Cache (miss) -> Memory

abstracts away hardware implementation details, software can be developed independent of hardware

wich function is callee

the function that called the next function

criteria for an embedded system?

cost, size and weight dependent, power consumption

Which of the following statements is TRUE regarding processes in operating systems?

Each process has its own heap and stack.

A recently accessed memory location is likely to be accessed again in the

defines architecture state, memory management, etc, interface between harware and software, programmers view of hardware

time required to access a level of hierarchy

Take advantage of Spatial Locality and Temporal Locality

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Answers

1
if we store A 0x12345678 in big endian system where wil 0x78 be stored
A+2
A+1
A+3
A
2
DMA is substitute for caches
True
false
3
what do you do if you want to pass alot of parameters to a function
put them in a register
just do it
put them in stack (pop)
4
“push” and “pop” What is the correct way to specify memory address for these instructions?
programmer needs to update SP after each push/pop instruction.
can have their address in any general purpose register.
SP is updated automatically
always have their address in Stack Pointer (SP)
5
what is stored in an ISA
number of registers
how big cache is
size of ram
number of instructions
6
What does DMA (Direct Memory Access) enable?
DMA allows input/output devices to access memory without CPU intervention
DMA allows CPU to access memory directly by bypassing the cach
All of above
DMA allows CPU to access hard disk directly
7
Virtual memory Safety: how to enable safe and efficient sharing of memory among multiple programs?
gives infinate memory to a process
To prevent user programs to access memory used by OS
control the access by one user program to the memory of other user programs
8
Spatial Locality
A recently accessed memory location is likely to be accessed again in the
Memory locations close to a recently accessed location are likely to be
9
where is special porpose registers?
r9 to r12
does not exist
r0 to r4
r13 to r15
10
When maximizing the time a system can operate without recharging the battery, the metric that we should optimize for is:
Performance
Energy
Energy Delay Product
Real Time Performance
11
Which of the following first two statements is TRUE
A process can go from "ready" to "blocked" state.
Both of the first two statements are FALSE
A process can go from "blocked" to "running" state
Both of the first two statements are TRUE.
12
Miss rate
time required to access a level of hierarchy
fraction of accesses that are hits at a given level of hierarchy
fraction of accesses that are miss at a givn level of hierarchy(1-hit rate)
13
what is wrong about Pipelined processor design
Executes only a phase (not whole instruction) in one cycle
Breaks instruction execution in different phases
Overlapping does not improve hardware utilization and performance
Executes only a phase (not whole instruction) in one cycle
14
Isolated IO
can use Load/store
special instructions to access IO
mapped to separate memory
same as port-mapped IO
15
Among write-back and write-through caches, which one is likely to write more data to memory
Write-through
Write-back
Both will always write the same amount of data to memory
16
Which of the following is defined by Instruction Set Architecture (ISA)?
The number of pipeline stages
The register width (i.e. the number of bits in a register)
The cache miss latency
The number of sets in the cache
17
what is Von Neumann architecture
split instruction and data memory
shared instruction and data memory
18
Why is the address bus unidirectional and the data bus is bidirectional?
The address is only used for memory accesses.
Data needs to go in one direction for write and in the other for read
I/O devices need to write and read to/from memory.
19
ISA does not define number of registers and the type of instructions
true
false
20
Dependencies and hazards are related concepts. Which of the following statements about them is true:
A dependency always generates a hazard in a CPU pipeline
RAW, WAW and WAR dependencies can turn into name hazards.
Branch prediction can help avoid dependencies.
Dependencies occur in the instruction stream, hazards occur in the pipeline
21
In ARM assembly programming, a "mov" instruction can be used to move an immediate value, say 45, to a register, say r3
Can we move a value of 1024 to a register using this same instruction? NO
Can we move a value of 1024 to a register using this same instruction? YES
22
what does execute
– Where the operands are
Read operands
Store result
Perform required operation
23
se bilde
Linker
Both Assembler and Linker are equally capable of resolving L2
Pre-processor
Assembler
24
can an ISA have multiple different implementations
true
false
25
which is callee registers and wich is caller
r0 to r3 = callee r4 to r12 = caller
r0 to r3 = caller r4 to r12 = callee
26
increasing performance of an existing embedded system does not provide any benefit
false
true
27
Machine dependent optimizations are aimed at a specific target architecture. Which?
Function inlining
Loop unrolling
Dead code elimination
All of the above are machine independent optimizations
28
which is true reguarding embedded systems
power not important
fixed performance requerements
designed for broad range
programable by end user
29
Let label “x” be an integer array? Which label loads the 3rd element into r1
c
a
d
b
30
single vs pipelined
Pipeline needs to be paused to avoid hazards
Cycle time in pipelined design is 3/1 of single cycle design
Cycle time in pipelined design is 1/3 of single cycle design
31
Which of the following is a valid number of ways in a set-associate cache?
5-way
3-way
8-way
32
Hit/miss in the brackets indicates whether the access resulted in a hit or miss in that structure.
TLB(hit) -> Page Table (hit) -> Cache (miss) -> Memory
TLB(hit) -> Cache (miss) -> page table (hit) -> memory
TLB(miss) -> Page table (hit) -> memory
TLB(hit) -> Cache (miss) -> Memory
33
What memory is cache
FLASH
SRAM
SREM
DRAM
34
why is ISA useful
converts software to harware by enabling different registers
makes software for specific hardware
abstracts away hardware implementation details
software can be developed independent of hardware
35
What does a TLB (Translation Lookaside Buffer) miss indicate?
The requested data is not in memory and needs to be brought from disk
The requested data is not in the cache but is present in the memory
None of the above.
virtual to physical trans for this address does not exist in the page table
36
If the physical memory size is doubled, how number of entries in the page table change? Assume a single-level page table
Number of entries remains same
Number of entries halves. (i.e. 0.5x)
Number of entries doubles. (i.e 2x)
Number of entries quadruples. (i.e. 4x)
37
Which one of the following first three statements is FALSE? If all three are true, choose the fourth option
Single-cycle design does not require hazard detection, prevention mechanism
All of the above are true
A pipelined processor operates on a higher frequency than a single cycle
pipelined N times faster than a single-cycle, N = number of pipeline stages
38
ARM Thumb 2 instruction set encoding contains:
32 bit instructions only
16 and 32 bit instructions.
16, 32 and 64 bit instructions.
16 bit instructions only.
39
wich function is callee
the function that called the next function
the function that got called
40
if we store A 0x12345678 in little endian system where wil 0x78 be stored
A
A+3
A+2
A+1
41
Let label “a” be an integer array with two elements? How does the array look like after executing the code.
[0, 2]
[0, 1]
[1, 0]
[2, 0]
42
Hvilken av følgende er ikke en fordel ved bruk av DMA til dataoverføringer, sammenlignet med å overføre data med CPU?
Det er mulig å sette CPU i sovetilstand selv om dataoverføringen er i gang
Strømforbruk kan gå ned
Det er lettere å programmere
CPU får bedre tid til å gjøre andre oppgaver
43
criteria for an embedded system?
cost
size and weight dependent
power consumption
44
Which of the following statements is TRUE regarding processes in operating systems?
All processes share the same heap and stack.
Each process has its own heap, but all processes share the same stack.
Each process has its own heap and stack.
Each process has its own stack, but all processes share the same heap
45
Find the bug in the following ARM Thumb-2 assembly code.
3
2
0
1
46
Temporal Locality
A recently accessed memory location is likely to be accessed again in the
Memory locations close to a recently accessed location are likely to b
47
what is an ISA
defines architecture state, memory management, etc
programmers view of software
interface between harware and software
programmers view of hardware
48
how do you load a value to register r2?
ldr r2, [#4, r3]
ldr r3, [#4, r2]
ldr r2, [r3, #4]
ldr r3, [r2, #4]
49
how big is a register
32bit
depending on system
64bit
16bit
50
Hit time
time required to access a level of hierarchy
fraction of accesses that are hits at a given level of hierarchy
fraction of accesses that are miss at a givn level of hierarchy(1-hit rate)
51
Memory hierarchy
Take only advantage of Temporal Locality
Take only advantage of Spatial Locality
Take advantage of Spatial Locality and Temporal Locality
all wrong
52
Cache organizations Direct mapped
A block can be placed anywhere in the cache
A block can be placed at one of the predetermined n locations in the cache
A block can be placed only by one location in the cache
53
Consider two processors, Processor A and Processor B, that implement the same i (ISA), same program
Both processors are guaranteed to operate at same frequency
Both processors are guaranteed to have same CPI (Clocks Per Instruction)
All of above are TRUE
Both processors are guaranteed to execute same number of instructions
54
Cache terminology miss
Must continue to search in the next level of hierarchy
data not found in cache
After data is eventually located, it is copied to thecache
55
what is Harward architecture
Separate memories for instruction and data
shared memories for instruction and data
56
where is SP
r15
r14
r12
r13
57
Which processor design is most likely to benefit from Branch Predictor
Pipelined processor design
Both single-cycle and pipelined design are likely to benefit equally
Single-cycle processor design
58
Cache terminology hit
data is found in cache (this is what we want to happen)
After data is eventually located, it is copied to thecache
Memory access completes quickly
data not found in cache
59
Which of the following is NOT defined by an Instruction Set Architecture (ISA)?
All of the above are defined by the ISA.
Instruction format (or encoding)
Cache size.
Number of registers.
60
how do you return from a finction?
mov r15, r14
mov r14, r15
61
what does decode
Perform required operation
What operation needs to be performed
Where the operands are
Read operands
62
cache access requires 1 cycle on a cache hit and 5 cycles on a cache miss, average memory access time at most 2 cycles
25% hitrate
70% hitrate
80% hitrate
75% hitrate
63
how many parameters can be passed to a finction
4 (r0 to r3)
12 (r0 to r12)
as many as you want
depends å number of registers
64
Hva er ikke riktig om exceptions?
En exceptionhandler kan ikke bruke stakken
Et interrupt er en vanlig form for exception
En exceptionhandler kjører i priviligert modus
65
What is an embedded system
any device that includes a programable computer
its a general purpous computer
has user end programmability
computing system specialized for a few aplications
66
The C tool flow has the following stages:
Preprocessor, compiler, assembler, and linker, in this order.
Preprocessor, compiler, prelinker, assembler, and linker, in this order.
Preprocessor, preassembler, compiler, assembler, and linker, in this order.
Preprocessor, compiler, prelinker, preassembler, assembler, and linker
67
Which one of the following first three statements is FALSE regarding volatile variables in C?
Compiler does not optimize away volatile variables as dead code
Volatile variables are not cached in processor caches
All above are true
Compiler does not reorder operations on a volatile variable
68
a = b + c ; e = a + d ; f = e + d ;
The code can be executed using at least two different registers.
The code can be executed using at least five different registers.
The code can be executed using at least four different registers.
The code can be executed using at least three different registers.
69
Cache terminology block (line)
data is found in cache (this is what we want to happen)
Memory access completes quickly
the unit of data stored in the cache
Typically in the ranges of 32-128 bytes
70
Which of the following events causes a transition from the user mode to the kernel mode?
Exception
Interrupt
Syscall
All of above
71
SRAM vs DRAM
SRAM = Lower cost
SRAM = Lower density
SRAM = Slower access (capacitor)
DRAM = No refresh required
72
What is the advantage of using an intermediate representation (IR) in a compiler?
Same compiler frontend can be used to translate any source language to IR
IR enables easier optimizations
All of the above
IR code is ISA independent
73
Virtual memory how to relieve programmers from dealing with limited main memory capacity?
To allow physical memory to be smaller than the program’s address space
To allow multiple programs to share limited physical memory
74
embedded system ALWAYS interact with the physical world
true
false
75
Why does locality exist in programs
it doesnt exist
Data working sets: arrays, temporary variables, objects
Instruction reuse: loops, functions
76
Miss penalty
time required to access a level of hierarchy
tme req to fetch block into some level from the nxt level dwn the hierarchy
fraction of accesses that are miss at a givn level of hierarchy(1-hit rate)
77
What is the advantage of multi-level page table over one-level page table?
Multi-lvl req less memory tan one-lvl for apps that dont use ful virt adres
Multi-lvl page table enables faster virtual to physical address translation
Both of the above.
78
Why is memory mapped I/O potentially a bigger problem on machines with 32-bit addresses than on machines with 64-bit?
Memory mapped I/O is a bigger problem in machines with 64 than in 32bit
64-bit machines transfer more data therefore, the overhead is lower.
32-bit addresses have smaller memory, therefore, they lose higher fraction
Machines with 64-bit addresses are faster
79
Branch instructions (conditional and unconditional) can jump forward and backwords?
true
false
80
what is Single cycle processor design
effective use of hardware resources
Cycles needs to be long enough to cover all functions
All functions (fetch, decode, …) are performed in one cycle
can run faster than pipelined
81
se bilde
A has a higher priority than B
B has a higher priority than C
C has a lower priority than B
C has a lower priority than A
82
what does and instruction format describe
location of source and destination operands/registers
both
opperation to be performed
83
Which one of the following first three statements is FALSE regarding embedded systems?
An embedded system is designed to run only a few applications
All of thea bove are true
Embedded systems are usually not programmable by the end user.
results arriving after the deadline are useless in hard real-time emb sys
84
how do you store value r2 to memory
str r3 [r2]
str r2 [r3]
85
Hva lagres i CPU-ens exceptionvektortabell?
Adresser (eller hoppinstruksjoner) til de forskjellige exceptionhandlerene
Statusinformasjon om en prosess som har blitt avbrutt av en exception
Prioriteringsinformasjon om de forskjellige exceptiontypene
Data om hvilken I/O-enhet som var årsaken til en exception
86
what granularity do we use at memory
word
byte
we can deside ourself by use of UINT_(bit size)
bit
87
wich access IO device as if it was memory
Isolated IO
memory mapped IO
both
88
NICE
69
69
69
69
89
Cache organizations n-way set associative
A block can be placed only by one location in the cache
A block can be placed at one of the predetermined n locations in the cache
A block can be placed anywhere in the cache
90
Find the bug in the following ARM Thumb-2 assembly code. Select the incorrect lines, if any
1
2
3
4
91
bl and b is the same
no
yes
92
grade memory by speed
1 DRAM, 2 Flash SSD, 3 Magnetic disk, 4 SRAM,
1 SRAM, 2 DRAM, 3 Flash SSD, 4 Magnetic disk
1 SRAM, 2 DRAM, 4 Flash SSD, 3 Magnetic disk
1 DRAM, 2 SRAM, 3 Flash SSD, 4 Magnetic disk
93
how do you add 5 to a value and store in r2?
add r3, r2, 5
add r3, r3, 5
add r2, r3, 5
add 4, r3, r2
94
Memory requirements,fast, large and high bandwith
cant have it
use memory hierarcy
buy large sram block
95
what does fetch
What operation needs to be performed
Where the operands are
Get instruction from (instruction) memory
Read operands
96
CISC ISA VS RISC ISA
RISC used in ARM and MIPS
CISC need more instructions
CISC used in x86
CISC has less registers (can do opperations in memory)
97
Hit rate
time required to access a level of hierarchy
fraction of accesses that are hits at a given level of hierarchy
fraction of accesses that are miss at a givn level of hierarchy(1-hit rate)
98
Cache organizations Fully associative
A block can be placed only by one location in the cache
A block can be placed anywhere in the cache
A block can be placed at one of the predetermined n locations in the cache
99
memory mapped IO
mapped directly to memory
same as port-mapped IO
can use load/store
eat up memory
100
where is link register
r13
r15
r0
r14

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