Unlike software, hardware circuits can execute (2038)

In parallel and at the same time

The values of all 32 MIPS registers are constantly being output. How do we read a register?

a 32-bit multiplexor selects the register

Field Programmable Gate Arrays are programmed (2078)

By establishing or breaking connections between devices

Twos-complement arithmetic is used because (2030)

Its circuits are the simplest & logic more easily translates

The two types of timing logic are (2072)

Level-triggered ad edge-triggered

How do synchronous SRAMs and Synchronous DRAMS differ from their asynchronous counterparts

They use the clock pulse to speed memory transfer

Clock pulse edges affect (2049)

When the state is read or written

A and B are adder inputs and Ci is the carry-in signal, which statement represents the result?

R = Ci & A & B | Ci & ~A & ~B | ~Ci & A &~ B | ~Ci & ~A & B

To check if 32 bits are all zero, what is typically done? (2035)

OR the bits and invert the output.

Verilog and VHDL are examples of (2020)

Software descriptions of hardware

If we build a four-bit adder with carry look ahead logic, what will be the case? (2040)

The ALU circuits will consume more power

The state held between traffic light cycles is (2071)

Which lights are red and which are green

A traffic light which switches state regardless if cars are at the stop lines is an example of

Moore machine and action based only on time

The purpose of a Karnaugh Map is to (2018)

derive a boolean expression from a truth table.

Is the building block for the MIPS 32-bit ALU.

In logic design, a set of data lines that is treated as a single logical signal is a(n)

Set of lines with multiple sources and uses

What is an example of clock skew? (2074)

Clock signal arriving at different circuit at different time

studbud

Appendix B Quiz

75 termsStudBud Administration221 plays

CS 2160 class quiz for appendix b (questions 538 - 621)

Flashcards75 cardsFPractice quizPHost liveL

Questions 75

Answers

1
A combinational logic circuit which has n inputs and 2^n outputs is a (2009)
Processor
Register
Recorder
Decoder device
2
Unlike software, hardware circuits can execute (2038)
correctly
when powered off
more accurately
In parallel and at the same time
3
Which is an example of a hardware description language (2020)
Logicore
Verilog
Forth
Assembly Language
4
Reading and writing on opposite clock-cycle edges (2050)
Used for instructions which cannot complete in one cycle
Decreases pipelining overhead
Increases power consumption
Lowers power consumption
5
In digital circuits, logic blocks are organized into two types (2004)
On and Off
AND and OR
Combinational and Stateful
void and non void
6
Truth tables always describe all possible input states (2005)
True
False
7
A hardware device that implements a logical sum of products is the (2012)
redundant array
Combinational Logic Block
PLA
Sequential block
8
The values of all 32 MIPS registers are constantly being output. How do we read a register?
a 32-bit multiplexor selects the register
By changing the phase of the input signal
A clock cycle is supplied to the desired register
A read signal is supplied to the desired register
9
Field Programmable Gate Arrays are programmed (2078)
By establishing or breaking connections between devices
by field technicians
By loading programs into the device's memory
by photo-etching.
10
The speed advantage of carry look ahead can be roughly obtained by counting and comparing
Gate delays
The number of times a carry signal is asserted
The number of input bits
The number of negations (NOTs)
11
What signals connect 1-bit adders together so that they can form 32-bit adders? (2027)
Carry-in and carry-out
add and subtract
Control lines
result lines
12
In logic, a sum is equivalent to a(n) (2011)
NOR
or
AND
NAND
13
Twos-complement arithmetic is used because (2030)
It was the first design and it worked well.
It consumes the least amount of power.
Its circuits are the simplest & logic more easily translates
It can be manufactured under less demanding conditions.
14
The two types of timing logic are (2072)
Level-triggered ad edge-triggered
Asserted and deasserted
Edge-triggered and pre-triggered
High- and low-triggered
15
The amount of time it takes an AND or an OR to execute is (2046)
the circuit lag
the clock skew
. proportional to power consumption
about the same
16
How do synchronous SRAMs and Synchronous DRAMS differ from their asynchronous counterparts
They use the clock pulse to speed memory transfer
They use critical-word-first access strategies
They use lower voltages
They do not need to enable chip read
17
How many combinations of Data A, Data B and Carry In produce a carry out signal? (2028)
One
4
Two
Eight
18
Clock pulse edges affect (2049)
How fast carries happen
The speed of combinational logic.
When logic becomes invalid.
When the state is read or written
19
Flip-flops and latches are the building blocks of (2050)
Circuits which hold state.
Arithmetic Logic Units
Inverters
Foreign policy
20
A and B are adder inputs and Ci is the carry-in signal, which statement represents the result?
Ci & (A | B) | A & (Ci | B) | B & (Ci | A)
Ci & A | Ci & B | A & B
R = Ci & A & B | Ci & ~A & ~B | ~Ci & A &~ B | ~Ci & ~A & B
~Ci & A & B | Ci & ~A & B | Ci & A & B | Ci & A & B
21
An inverted OR is a(n) (2008)
Additional Gate
nor
NOT
NAND
22
A static RAM has 4M 8-bit entries. How many input address lines does it have? (2058)
12
Twenty two
18
8
23
The carry out signal for a 1-bit ALU with inputs A, B and carry in (C) is expressed by (2039)
(A|C) & (B|C)
(A|B) & (A|C) & (B|C)
(A&B) | (A&C) | (B&C)
A | B | C
24
The basic boolean algebra operators are (2006)
Equal and Not Equal
&, |, ~
&, | ^
Or, Nor and Xor
25
The basic component of the logic block circuit is the (2008)
Drain
and/or/not gates
Fence
conductor
26
Which is not a building block of an Arithmetic Logic Unit (2026)
AND gates
OR gates
Outputs and Inputs
Multiplexors
27
To check if 32 bits are all zero, what is typically done? (2035)
OR the bits and invert the output.
Invert the bits and AND them.
Invert the bits and OR them.
ADD 1 and see if the result is still 1.
28
Verilog and VHDL are examples of (2020)
Software descriptions of hardware
Internet security companies
ALU designs
motherboard manufacturers
29
If we build a four-bit adder with carry look ahead logic, what will be the case? (2040)
The circuit can provide more functions
The ALU circuits will consume more power
The circuit is easier to build
The circuit will consume less power
30
Not (A OR B) equals (NOT A AND NOT B) (2031)
True
False
31
Almost all digital circuits can be represented with (2008)
Multiplexors
Addition and Subtraction
AND, OR and NOT gates
flip flops
32
A digital circuit which reproduces a truth table is an example of ______ logic (2009)
Combinational
Truthful
Stateful
Moore
33
The state held between traffic light cycles is (2071)
How many cars are at the stop line
The next state the light should go to
Which lights are red and which are green
A history of the last light changes
34
All logic circuits can be constructed with and, or and ____ gates (2008)
Combinational
Stateful
Stable
not
35
A traffic light which switches state regardless if cars are at the stop lines is an example of
Turing machine
Moore machine and action based only on time
Mealy machine
Mindless policy
36
If a < b and we perform the operation (a-b) the final one-bit adder's carry out will be
Don't Care
One
Upset
Deasserted
37
The design for a 32-bit Arithmetic Logic Unit is based on (2027)
Multiple 1-bit ALUs
32 multiplexors
Eight input lines and eight output lines
32 AND gates and 32 OR gates
38
Logic system whose blocks don't contain memory and compute the same output given the same input
Combinational
Dubious logic
Stateful logic
Organizational logic
39
The purpose of a Karnaugh Map is to (2018)
Program a Field Programmable Gate Array
Map inputs to outputs
derive a boolean expression from a truth table.
Determine whether or not two truth tables are the same
40
A 1-bit ALU (2026)
Is the building block for the MIPS 32-bit ALU.
Is built as an academic exercise, but has no practical use.
Is low-powered enough to be used in mobile devices.
Does not scale well to 32 bits
41
What four functions are performed by every arithmetic logic unit (2030)
AND, OR, add, subtract
Add, subtract, multiply, divide
Zero, result, compare, control
Add, subtract, branch, jump
42
An unused output or input is called a(n) (2017)
Don't Care
Waste of time and space
Unused output or input
Degree of freedom
43
An inverted AND is a(n) (2008)
nand
Inclusive Gate
NOR
Exclusive Gate
44
The difference between a Programmable Logic Array (PLA) and a Read Only Memory (ROM) is
The PLA does not scale well.
PLAs are not efficient at handling large numbers of input
The ROM does not scale well.
PLA retains its ability to function after the power cycled
45
A circuit that takes a set of input bits and produces a prestored set of output bits is a(n)
Programmable Gate Array
ROM-Read Only Memory
Register
Combinational Logic Block
46
A finite state machine uses sequential logic (2067)
False
True
47
What logic circuit is used to write data to the register file? (2056)
Voltage regulators
OR gates
An encoder
AND gates and a decoder
48
In a 32-bit MIPS system, SRAM chips often store all 4 bytes of a word on the same chip (2058)
False
True
49
In logic design, a set of data lines that is treated as a single logical signal is a(n)
Loop
Path
Trace
Set of lines with multiple sources and uses
50
What is an example of clock skew? (2074)
Clock signal arriving at different circuit at different time
One circuit completes its calculation before another
A biphase clock signal where one rising edge is behind
The fact that clock periods aren't always the same length
51
Carry look-ahead is often done in group of ____ bits (2045)
8-10
16
Four
8
52
Error correction requires multiple bits while error detection requires only one (2066)
False
True
53
What slows down the speed of a 32-bit adder? (2038)
The complexity of the process.
Ripple carry
The magnitude of the input variables.
Parity checks.
54
Which circuit element selects one of a number of inputs depending on a control signal? (2010)
Arithmetic Logic Unit
Multiplexor
AND gate
flip flop
55
A multiplexor can be built from three gates: (2010)
Three NOR gates
an OR gate and two AND gates
Three NAND gates
Two OR gates and an AND gate
56
In order to assure proper sequencing and timing of operations, Verilog uses a process called
Locking
blocking
Forking
Coalescing
57
If a synchronous signal is not sampled at the proper time what can characterize the output?
Uncorrelated state
Metaphysical state
Metaphorical state
Metastability or an indeterminate state
58
Edge triggering is (2048)
Ineffective at low clock frequencies.
Phase gated
Sequential
When the clock edge signals state change
59
Storing data for 32 32-bit registers requires (2055)
16 clock cycles
1024 bits or One kilobit of SRAM
64 clock cycles
512 flip-flops
60
A one-bit adder could be implemented with a read-only memory having (2027)
An input and an output
Five control lines
Four inputs and three outputs
Three inputs and two outputs
61
A latch can change state on the falling clock edge (2051)
False
True
62
The MIPS processor logic could be expressed in Verilog (2023)
False
True
63
A traffic light which switches state based on if cars are at the stop lines is an example of
Turing machine
Mean machine
Mealy machine or combinational logic circuit
Data storage circuit
64
A state machine is a combinational logic device (2067)
True
False
65
Multiplexors can be decomposed into (2010)
Sequential logic
AND and OR gates
FPGAs
Ones and zeroes
66
A flip-flop changes state (2051)
When its state is read
On clock failure
On the clock edge
Whenever inputs change
67
What method is typically to test (a == b)? (2035)
Branch on equal and see if the branch is taken.
Branch on not equal and see if the branch is taken.
Negate b, add to a, see if the Zero output is asserted
Perform (a + b) and see if the result is 0
68
Addition, subtraction, logical ANDs and ORs are performed by the (2026)
Sign Extender
Cache
ALU
Multiplexor
69
Which is not a 1-bit ALU input or output (2029)
Result
Chip enable and Select
Carry in
Operation
70
Clock skew is characterized by (2074)
The power required to run the clock
clock pulse arriving at multiple locations at different time
Unequal rise times in adjacent clock pulses
relativistic effects due to the speed of the machine
71
Which concepts are most closely related? (2004)
Assert and false
truth tables and logic equations
Logical OR and multiplication
Addition and the logical AND
72
The chief difference between a programmable logic device and a field programmable gate array is
The PLD is combinational while the FPGA is stateful
FPGAs are smaller
The PLD bas both memory and logic
FPGAs are combinational circuits
73
Under what situation is the least-significant carry-in set to 1 and is Data B inverted?
Finding the next value of the program counter
Subtracting B from A
Performing ones-complement arithmetic
Performing long division
74
If a 32-bit adder performs the operation (a-b) and the bit-31 carry out is zero, what is true
a > b
This will never happen
a !=b
a >= b
75
Group of logic elements that contain memory and value depends on the inputs and current memory
Sequential
Combinational logic
Parallel logic
Amnesic logic

Appendix B Quiz Flashcards | StudBud