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Verilog
Verilog
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StudBud Administration
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This quiz is based on concepts of Verilog Programming.
Flashcards
10 cards
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Practice quiz
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Questions
10
Answers
1
User Constraint File extension in Vivado is
.xcd
.xdc
.bit
.ucf
2
What is the default value for reg data type
0
1
x
z
3
The operating voltage level of Nexys 4DDR and Zybo is
5.0V, 3.3V
5.0V, 5.0V
3.3V, 1.0V
3.3V, 3.3V
4
'timescale 10ns/100ps #10 in testbench will give us
10ns delay
100ns delay
1000ns delay
100s delay
5
Schematic that user understand is available in
Design Source
Design Synthesis
RTL Synthesis
Behavioral Simulation
6
Testbench for Half Adder contains how many I/O ports
Three
Four
Zero
Two
7
Verilog is
Case Sensitive
Can't Say
Case Insensitive
8
Suggest best modeling style to implement 4:1 Mux
Behavioral Modeling
Switch Level Modeling
Structural Modeling
Gate Level Modeling
9
@posedge means
Transition from 1 to X
Transition from 0 to X
Transition from 1 to 0
Transition from 0 to 1
10
Initial Statement is
Non-Synthesizable
Can't say
Synthesizable
